1. Field of the Invention
The present invention relates to a DC offset cancel circuit, a semiconductor device, and a receiving device, and more particularly, to a DC offset cancel circuit, a semiconductor device, and a receiving device including an I-channel and a Q-channel that are perpendicular to each other.
2. Description of Related Art
In recent years, high sensitivity and high accuracy in a receiving IC (Integrated Circuit) of a GPS (Global Positioning System) have been among the most significant problems in forming a GPS receiving device. Therefore, there is an increasing demand for improving the performance of an analog-digital converter (hereinafter referred to as ADC) that converts a received analog signal to a digital signal processed by a base band IC.
On the other hand, manufacturing variations due to miniaturization of semiconductor device manufacturing processes for achieving downsizing and low power consumption should not be negligible. When a DC offset component of a differential signal input to the ADC increases due to the relative variation, the ADC cannot normally convert analog signals to digital signals. This leads to degradation of the receiving sensitivity and the receiving accuracy of the GPS receiving device. The mechanism of this phenomenon is explained with reference to FIGS. 5 to 7. FIG. 5 is a block diagram showing the occurrence of a DC offset component in an ADC. FIG. 6 is a graph showing input/output signal waveforms of the ADC when there is no DC offset component. FIG. 7 is a graph showing input/output signal waveforms of the ADC when there is a DC offset component.
As shown in FIG. 5, a signal I (or signal Q) and a signal Ib (or signal Qb) are input to an ADC 20 in an I-channel side (or Q-channel side). The signal I (or signal Q) and the signal Ib (or signal Qb) are differential signals. The ADC 20 converts the signals to two-bit signals and outputs the signals as an output signal Imag (or output signal Qmag) and an output signal Isign (or output signal Qsign). At this time, a DC offset component ΔVin is generated between the signal I and the signal Ib.
In this configuration, the output signal Imag and the output signal Isign are generated. The output signal Imag is the two-bit output signal generated by comparing the signal I with a threshold voltage Vth. The output signal Isign is the two-bit output signal generated by comparing the signal I with the signal Ib. In this configuration, when there is no DC offset component, for example, the duty ratios of the output signal Imag and the output signal Isign are 50:50 as shown in FIG. 6. On the other hand, when there is a DC offset component ΔVin corresponding to 30% of the amplitude, for example, in this configuration, the duty ratios of the output signal Imag and the output signal Isign vary as shown in FIG. 7. In this case, the duty ratio of the output signal Imag is 62:38, and the duty ratio of the output signal Isign is 55:45. In summary, the presence of the DC offset varies the duty ratio of the digital signal output from the ADC, which degrades the signal quality. This causes degradation of the receiving sensitivity and the receiving accuracy of the GPS receiving device.
Take an LSI for GPS (Large Scale Integration) as an example, a method of reducing the DC offset component is explained. FIG. 8 is a block diagram of a DC offset cancel circuit 300 in AK1518 which is the LSI for GPS (“LSI for GPS AK1518”, [online], ASAHI KASEI MICRODEVICES CORPORATION, [searched on Sep. 8, 2009], Internet <URL:http://www.asahi-kasei.co.jp/akm/japanese/product/ak1518/ak1518.html>). As shown in FIG. 8, the DC offset cancel circuit 300 includes a mixer 21, an IF unit 22, and an ADC 24 connected to each of an I-channel side and a Q-channel side. The IF unit 22 is the amplifier having a gain of A times. The ADC 24 is the two-bit ADC. Further, the signal components of the I-channel and the Q-channel are perpendicular to each other.
The IF unit 22 includes an IF amplifier 31, an IF-LPF (Low Pass Filters) 32, and an IF-AGC (Automatic Gain Control) amplifier 33. The output of the IF unit 22 is connected to input parts of a DC offset cancel amplifier 26 and the ADC 24.
The DC offset cancel amplifier 26 is the amplifier having a gain of B times. The DC offset cancel amplifier 26 has an output corresponding to a signal I connected to an input corresponding to a signal Ib of the IF unit 22. An output corresponding to the signal Ib is connected to an input corresponding to the signal I of the IF unit 22. An output corresponding to a signal Q is connected to an input corresponding to a signal Qb of the IF unit 22. An output corresponding to the signal Qb is connected to an input corresponding to the signal Q of the IF unit 22.
The ADC 24 in the I-channel side outputs an output signal Imag and an output signal Isign. The ADC 24 in the Q-channel side outputs an output signal Qmag and an output signal Qsign.
Subsequently, an operation of the DC offset cancel circuit 300 will be described. The DC offset cancel circuit 300 generates four-phase signals whose phases are shifted by 90° each other. The mixer 21 in the I-channel side generates the signal I (0° and the signal Ib (180° that are differential signals according to an RF signal and an LO signal that are input, and outputs the generated signals to the IF unit 22. The mixer 21 in the Q-channel side generates the signal Q (90° and the signal Qb (270° that are differential signals that are perpendicular to the I-channel side according to the RF signal and the LO signal that are input, and outputs the generated signals to the IF unit 22.
The IF unit 22 amplifies the signal I, the signal Ib, the signal Q, and the signal Qb and outputs the amplified signals to the DC offset cancel amplifier 26 and the ADC 24.
The DC offset cancel amplifier 26 extracts a direct-current component of the output corresponding to the signal I of the IF unit 22 and feeds back the direct-current component to the input corresponding to the signal Ib of the IF unit 22. Further, the DC offset cancel amplifier 26 extracts a direct-current component of the output corresponding to the signal Ib of the IF unit 22 and feeds back the direct-current component to the input corresponding to the signal I of the IF unit 22. Similarly, the DC offset cancel amplifier 26 extracts a direct-current component of the output corresponding to the signal Q of the IF unit 22 and feeds back the direct-current component to the input corresponding to the signal Qb of the IF unit 22. Further, the DC offset cancel amplifier 26 extracts a direct-current component of the output corresponding to the signal Qb of the IF unit 22 and feeds back the direct-current component to the input corresponding to the signal Q of the IF unit 22. Accordingly, the DC offset components between the signal I and the signal Ib and between the signal Q and the signal Qb are cancelled.
The ADC 24 outputs the output signal Imag, the output signal Isign, the output signal Qmag, and the output signal Qsign that are two-bit digital signals based on the input signals.
In short, the DC offset components generated in the mixer 21 and the IF unit 22 are independently cancelled by the I-channel and the Q-channel, respectively. As described above, the gain of the IF unit 22 is A, and the gain of the DC offset cancel amplifier 26 is B. Accordingly, the DC offset component ΔVout in the output part of the IF unit 22 corresponding to the DC offset component ΔVin generated between the signal I and the signal Ib is expressed by the expression (1).ΔVout=1/B×ΔVin  (1)
When the DC offset cancel amplifier is not employed, the expression (1) is ΔVout=A×ΔVin.